This invention relates to phase-locked loops (PLL's), and more particularly to built-in test circuits for PLL's.
Many of today's complex electronic systems operate synchronously and require generation of one or more clocks. Phase-locked loops (PLL's) are often employed to generate such clocks from a clock source such as a crystal oscillator. While PLL's can be sold as stand-alone integrated circuit (IC) chips, often PLLs are integrated with many other circuits on a very-large-scale-integration (VLSI) chip.
The cost of manufacturing such IC chips is related to the manufacturing yield. Yield is limited because small particles such as dust can land on the surface of the chip during processing, resulting in a point defect. Other causes of such point defects may include impurities in manufacturing chemicals and materials. The number of defects in a device is often proportional to the area of the device. For example, a large-area capacitor is more likely to have a point defect than a smaller capacitor.
FIG. 1 shows a PLL on a chip. Chip 10 may be integrated with a larger system or may be sold as a stand-alone PLL chip. Clock source 18 generates a reference clock CLK that is input to chip 10. This reference clock passes through input buffer 22 and is compared in phase to a feedback clock FB that passes through input buffer 24. Phase comparator 12 compares the phases of CLK and FB and activates charge pump 14 to charge or discharge filter capacitor 20. As capacitor 20 is charged or discharged, the voltage across capacitor 20 changes, and voltage-controlled oscillator VCO 16 senses the capacitor voltage and adjusts the output frequency of an output clock that is buffered by output buffer 26. The feedback loop may be external as shown, or an internal feedback loop may be substituted.
Typically a large capacitance is required for capacitor 20 in order to sufficiently filter time-varying phase differences. The large area required by capacitor 20 can make it particularly prone to point defects. For example, a contaminating particle in the oxide between the plates of capacitor 20 can cause leakage or even a short between the plates of the capacitor.
Chip 10 may be tested by applying inputs (stimuli) and observing outputs such as the FB output from VCO 16. When a defect such as a short occurs on capacitor 20, the voltage input to VCO 16 may be insensitive to the input from phase comparator 12, and the feedback output may not change as expected as VCO 16 may be stuck at a low frequency.
While major defects causing direct shorts on capacitor 20 may be easy to detect at the outputs of chip 10, smaller defects may be harder to detect. When a point defect is smaller and causes some leakage between the plates of capacitor 20, the voltage into VCO 16 may still vary somewhat as phase comparator 12 detects phase differences in the inputs to chip 10. When leakage is very small the current supplied by charge pump 14 may overwhelm the leakage current, making operation appear normal during testing. Small amounts of leakage can especially be masked during high-speed testing when charge pump 14 is rapidly charging and discharging capacitor 20. Such minor leakage may only be noticeable during unusual conditions such as when the feedback clock and reference clock remain in phase for long periods of time.
Thus smaller defects that cause relatively minor leakage currents from capacitor 20 may not be detected during normal testing. Failures may later occur when chip 10 is placed in a system and operating conditions are such that charge pump 14 remains off for unusually long periods of time. These sporadic failures may be extremely difficult to detect and may cause intermittent system failures resulting in hard-to-discover bugs.
What is desired is a built-in circuit for testing the PLL capacitor. A test circuit that directly tests the PLL capacitor is desired. A test circuit that can more accurately test the filter capacitor and can detect small leakage currents from the capacitor is desirable.